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L26: Power Estimation. Battery technology. Microprocessor power dissipation. Power(W). Alpha 21164. Alpha 21264. 50. P III 500. 45. P II 300. 40. 35. Alpha21064 200. 30. 25. P6 166. 20. P5 66. 15. P-PC604 133. 10. i486 DX2 66. P-PC601 50. i486 DX25. 5. i386 DX 16.

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L26: Power EstimationBattery technologyMicroprocessor power dissipationPower(W)Alpha 21164Alpha 2126450P III 50045P II 3004035Alpha21064 2003025P6 16620P5 6615P-PC604 13310i486 DX2 66P-PC601 50i486 DX255i386 DX 16i486 DX4 100i286i486 DX 50P-PC750 40019801985199019952000yearCapacity(Watt-Hour/lb)5040Is it possible?3020Nickel-Cadmium1019751985199520001965yearCost vs PowerPowerStrategyCostLow powerprocessornonenone1 Wattheat sink,air flow$1-53-5 WattLaptopComputerfan sink$10-155-15 Watt15+ Wattexotic$50+Power EstimationCircuit Level Power Estimation Logic/module Level Power Estimation High Level Power Estimation Software Power Estimation Power Estimation TechniquesCircuit Simulation (SPICE): a set of input vectors, accurate, memory and time constraints Monte Carlo: randomly generated input patterns, normal distributed power per time interval T using a simulator switch level simulation (IRSIM): defined as no. of rising and falling transitions over total number of inputs Powermill (transistor level): steady-state transitions, hazards and glitches, transient short circuit current and leakage current; measures current density and voltage drop in the power net and identifies reliability problem caused by EM failures, ground bounce and excessive voltage drops. DesignPower (Synopsys): simulation-based analysis is within 8-15% of SPICE in terms of percentage difference (Probability-based analysis is within 15-20% of SPICE). Power Estimation TechniquesStatic (non-Simulative) - useful for synthesis and architectural exploration Probability-based Entropy-based Dynamic (simulative) - useful for final power Direct Sampling-based Compaction-based Hybrid (high-level simulation + low-level analytical model evaluation) Power macromodels for datapath, control, memory Instruction-level models for microprocessors, DSPs Previous work(1)Simulation based approach accurate and system independent pattern dependent and after implementation Direct simulation SPICE, transistor-level simulator, IRSIM Statistical simulation Monte Carlo simulation Previous work(2)Non-simulation based approach library, stochastic, information theoretic model Behavioral-level approach library(parameter, area, delay, internal power dissipation) useful in comparing different adder and multiplier architecture for their switching activity stochastic using probability density function, joint probability density function. Information theoretic entropy Previous work(3)Logic-level approach using signal probability zero-delay based approach OBDD Circuit LevelSPICE classical tool for power analysis of circuits large runtime for large circuits mainly used as the reference for other power estimation tools. PowerMill uses simplified electrical model of the transistor. operating conditions of transistor are stored as look-up tables.(interpolated by piecewise linear approximation.) stages - partitioned subcircuits, source/drain connected transistors 2-3 orders faster than SPICE IntroductionGlitch additional power is typically 20% Circuit LevelIRSIM event-driven, switch-level simulator modeled by capacitive nodes and transistors partitioning into stages is used. voltage level - High, Low, Undetermined Partitioning into stagesTheoretical backgroundSynchronous system controlled by global clock Hierarchical approach to power estimation of combinational circuits(1)Estimate power of large circuit in a short time model sub-circuit compute steady-state prob. compute edge-activity using state-transition-diagram(std) compute energy State-Transition Diagram 2 input NOR Hierarchical approach to power estimation of combinational circuits(2)Hierarchical approach to power estimation of combinational circuits(3)Computation of steady-state prob. Compute edge prob. Make state-transition matrix Compute steady-state prob. Compute edge-activity Energy computation of each edge in the std Compute edge activity energy using SPICE Hierarchical approach to power estimation of combinational circuits(4)Computation of output signal parameters compute x3 using std of NOR 1compute energy for second NOR using Wj calculatedNOR 1 and EAj obtained for the second NORHierarchical approach to power estimation of combinational circuits(5)Loading and routing considerations Recompute edge energy with concerning of load cap. Effect of loading can be taken into account Power estimation of sequential circuitsSequential block has a combinational block and some storage elements like flip-flop Extend method to flip-flop Experimental result(1)Power estimation of basic cells and multipliers Logic LevelPattern dependent analysis example : Entice-Aspen System(‘94 Workshop on Low Power Design) cell characterization using SPICE simulation under different conditions parameters : supply voltage, input signal slope, operating temperature, fabrication process variation modeling styles : polynomials, tables, piecewise linear power vector : Set of logic values and signal transitions activity analysis using Verilog-XL simulator find event vector in the power vector set total energy = (Energy of power vector)(# of occurrences) High Level Power EstimationRTL power estimation problem given an RTL circuit description consisting of m modules, and an input vector sequence of length N, estimate the average power consumption estimation process perform behavioral simulation and collect the input statistics for all modules in RTL descriptions evaluate the power macro-model equation for each module and sum over the modules implementation in the form of a power co-simulator collect input statistics from the output of behavioral simulator produce the power value at the end Power macro modelcensus macro modelingsampler macro modelingadaptive macro modelingCensus macro modelinginput data statistics must be collected for every simulation cyclevery slow simulationassumed input vectorsmacro-model is biasedex) pseudo-random, speech data, etc.requiresinput vectorsPowerestimateInputvectorsPowerestimateBehavioralSimulatorSamplerMacroModelingrequiresinputvectorpowerBehavioralSimulatorCensusMacroModelingGate-levelPowerSimulationinput vectorsforeach moduleConfidence leveland intervalInputvectorsinput vectorsfor each modulevectorsconfidenceleveland intervalHigh Level Power EstimationSampler macro modelingcollects and analyzes input vectors for a relative small number of cyclesusing statistical random sampling methodsAdaptive macro modelinginvolves a gate-level simulator on a small number of cyclesimprove the estimation accuracybias of the static macro models is reducedHigh Level Power EstimationHigh Level Power EstimationPower estimation at high level statistical technique only consider the operations of a given type, number of bus, register and memory access power dissipation depends on data activity physical capacitance two approaches considering physical cap. develop analytic models for estimating the switched capacitance synthesis the circuit and then estimate the power dissipation of the circuit Develop analytic modelsdevelop analytic models for estimationmodels is a function of the circuit complexity and technology/library parameterskey issueestimation of the circuit complexitySynthesis approachprocedurequick synthesisestimate power dissipation using RTL/gate-level estimation techniquestends to be more accuraterequires the development of a quick synthesis capabilitymuch more efficient than a full synthesis program in timeHigh Level Power EstimationSoftware Power EstimationObjective estimate the power dissipation of a piece of code Lower level method gate level power estimation Higher level method architectural power estimation bus switching activity instruction level power analysis Gate level power estimationmost accurate methodtoo slow approachusefulnessevaluate the power dissipation behavior of a processor designcharacterize the processor for the more efficient instructionArchitectural power estimationless precise but much fastdetermine which system components are active in each execution cycleBus switching activitybus activity is assumed to be representative of overall switching activitycomputed from the sequence of op-codes, addresses, and dataInstruction level power analysischaracterize the power dissipation of instruction sequenceuse for optimizing a program based on the power estimate Software Power EstimationInstruction level power analysisbase costindependent of the prior state of the processorcircuit state effectstake into account the effect of prior processor stateInstructionNameBaseCost(pJ)Circuit State Effects (pJ)LOADDLOADADDMULTLOAD;ADDLOAD;MULTLOAD1.980.130.151.190.921.251.06DLOAD2.370.171.190.921.321.06ADD0.990.260.530.860.99MULT1.190.660.790.96LOAD;ADD2.100.400.53LOAD;MULT2.250.79Software Power EstimationCircuitStateInstructionBaseDLOAD A<-x, B<-y2.371.19LOAD C<-x; MULT D<-A,B2.251.060.99ADD A<-C,D0.99Total5.613.24 Power OptimizationModeling and Technology Sources of power consumption Switching component Short-circuit component Leakage component Static power Voltage Scaling Adiabatic switching Circuit Design Level Logic and Module Design Level Architecture and System Design Level Some Design Examples Switching componentenergy for charge parasitic capacitors(gate, diffusion, and interconnect) ex1. In CMOS, output nodes are charged or discharged. ex2. Charge sharing PMOSnetworkHighNMOSnetworkLowEvaluationShort circuit componentfinite rise and fall time direct current path between Vdd and GND (Both NMOS and PMOS are turned on)VinIsIsVint1t2Leakage componentreverse viased PN junction subthreshold current GateGndP+P+NReverse leakage currentVddStatic poweralthough CMOS circuits consume power only when switching, some situations consume static power. reduced voltage levels feeding CMOS gates pseudo-NMOS logic style single PMOS pullup network(always ON because the gate is grounded) when the output is driven low, conducting path from the supply to ground is created. Vdd-VtnVddWeakly turned onVddVoltage ScalingWhy? Lowering the supply voltage is most effective means of power reduction. Feature size of the process geometry decreases. Smaller process geometry requires the voltage to be lowered because of the thinner gate. Although the delay increases as the voltage is lowered, the small channel length of the advance process increases the circuit performance Voltage ScalingScaling from 5V to 3.3V External components(TTL) operate at 5V and the cost to interface with them made the voltage scaling difficult. The components from low-voltage industry such as LVTTL, CMOS, BiCMOS(which operate at 3.3V) make the voltage scaling with low cost. Scaling below 3.3V Depending the technology, the supply voltage can be lower than 3.3V. The supply voltage cannot be too close to the threshold voltage. significant speed loss. Performance vs. Voltage scalingThe lowest voltage possible without significant loss of performance is the voltage when the electron velocity get out of saturation. As the feature size is shrunken, the same electric field can be obtained even when the supply voltage is decreased. ( i.e, velocity saturation occurs at the lower supply voltage. ) electronspeedTerminal speedAs process technology is shrunkenSupply voltageAdiabatic SwitchingEnergy injected into a node with cap. C to a voltage, V, is Esig = CV2/2 Energy drawn from the power supply Einj = QV = CV2 Einj = 2 Esig : Half of the energy drawn from the supply is dissipated Also, Esig is dissipated when the node pulled low. All energy drawn from the supply is used only once before being discarded. Adiabatic SwitchingSolution : charge the load from a supply that is at the same potential as the load Same supply voltage as the voltage of the load Charge transfer proceeds sufficiently slowly to not require a large potential drop Energy dissipation varies roughly with the inverse of the switching time Difficulties switching transitions must occur when there is no potential drop across the switching devices zero energy occurs with arbitrarily low speed switching : With realistic switching rates, the energy savings may not sufficient compared to the circuit complexity. Adiabatic SwitchingVaXX’VaY’YExample : inverter 1. input(X, X’) set to a value value. 2. (evaluation) slow voltage ramp to Va from 0 to Vdd. One of Y and Y’ is adiabatically charged to Vdd. 3. (hold) Y and Y’ can be used as the inputs of other stage 4. (restore)ramp to Va from Vdd to 0. XYX’XXX’X’Y’Adiabatic SwitchingOther components of power consumption on-resistance of switches Process improvement(parasitic capacitance reduction) allows lower power consumption in adiabatic circuits Application When a small number of circuit nodes which significant capacitance driven by high voltage. Capacitive transcducers, LCD panels, etc. Reduction of Switched CapacitanceReduce the switching activity of the digital circuits to the minimal level required to perform the computation saves the power. Methods power down mode of the chip gated clock circuit optimization to reduce transitions reduction of # of operations(algorithm change) data representation resource ordering logic style : Dynamic or Static layout optimization

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