A CMOS Integrated Linear Voltage to Pulse Delay Time Converter for Time Based Analog to Digital Converters

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A CMOS Integrated Linear Voltage to Pulse Delay Time Converter for Time Based Analog to Digital Converters
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  A CMOS Integrated LinearVoltage-to-Pulse-Delay-Time Converter for TimeBased Analog-to-Digital Converters Holly Pekau, Abdel Yousif, James W. HaslettDepartment of Electrical and Computer Engineering, University of Calgary, Calgary, Canada, T2N 1N4TRLabs, Calgary, Canada, T2L 2K7 (haslett@enel.ucalgary.ca)  Abstract —A novel  0 . 13 µm  CMOS integrated linear voltageto pulse delay time converter (VTC) is proposed. The VTCarchitecture uses current starved inverters where the inverterdelay versus input voltage characteristic is linearized by usingseveral parallel current starving devices with different gate biasvoltages and different amounts of source degeneration. The VTCoperates at a clock frequency of up to 500 MHz. Input voltagesignals of up to 2 GHz can be converted to pulse time delaysby using several VTC’s in parallel. Since the voltage to timeconversion is essentially done with a single inverter stage nosample-and-hold is needed for the input voltage. The VTC canbe used in combination with a time-to-digital converter (TDC) tobuild a simple high speed, low power, time based analog-to-digitalconverter (ADC) that consumes very little chip area. I. I NTRODUCTION The need for high-speed low-power ADC’s for softwareradio receivers has led to the development of a new type of time-based ADC’s where the input voltage is first convertedto a pulse delay time using a voltage-to-time converter (VTC),and then the pulse delay time is converted to the digital domainby a time-to-digital converter (TDC) consisting of digitallogic and counter circuits [1]. This type of time based ADCcan operate at very high clock and input frequencies whileconsuming less power and die area than other high frequencyADC architectures. Time based ADC architectures can also bemade reconfigurable for use in multi-standard software radioreceivers.Several high speed VTC’s for various applications have beenproposed by previous authors. Most of these VTC’s are basedon the simple current starved inverter shown in Fig. 1 wherethe input voltage  v in  controls the delay of the falling edgeof the clock signal ( v clk ) through the inverter by changingthe equivalent resistance between the source of the inverterNMOS device and ground. In [2] Djemouai et al propose abasic current starved differential delay cell and add weak crosscoupled inverters to the cell to shorten the transition times of the inverters in [3]. Dudek et al propose a similar VTC but adda weak nfet with its gate tied to the supply to ensure the VTCoperates at very low input voltages [4]. Watanabe et al proposea delay unit consisting of a series of inverters with the PMOSsources tied to the input voltage [1]. Gray et al propose inverterdelay units where the clock drives the gates of the NMOSdevices and the delay is controlled via the bias voltages of the M1M2M3V clk  V in V clk-delayed Fig. 1. Basic current starved inverter schematic PMOS gates resulting in higher current consumption but lowerswitching noise [5]. These previously published VTC’s weredesigned for various applications but are not suitable for usein a high speed high resolution time based ADC with minimaldigital post processing because they are not sufficiently linearand the voltage to time conversion is not sufficiently sensitive.In this work we present a VTC with a novel linearizationscheme that results in improved linearity and higher voltagesensitivity for time based ADC applications.II. C IRCUIT  D ESIGN A simplified schematic of the VTC circuit designed in a 0 . 13 µm  CMOS process is shown in Fig. 2. Current starvingof the inverter transistors M1, M2, M3, and M4 is done usingtransistors M5, M6, and M9-M14. The gates of M11-M14 areAC coupled to the input signal (not shown) to allow them to bebiased at different voltages than the gates of M5 and M6. M7and M8 are used for source degeneration of current starvingdevices M5 and M6. M9 and M10 are weak devices with smallaspect ratios and low  g m ’s used to ensure the inverter operatesat very low input voltages. Weak cross coupled inverters withsmall aspect ratios are connected between the output invertersto allow for faster pulse transition times. Additional invertersare used as output buffers to allow the VTC to drive thecapacitive load of the output pads. The layout of the VTCin a  0 . 13 µm  CMOS process is shown in Fig. 3. 2373 ISCAS 2006 0-7803-9390-2/06/$20.00 ©2006 IEEE  v clk   v clk  v clkdelay v clkdelay v in  v in V DG  V DG M1M2M3M4M5 M6M7 M8M9 M10M11 M12M13 M14 Fig. 2. Simplified VTC schematic (gate biasing not shown)Fig. 3. VTC layout in a  0 . 13 µm  CMOS technology ( 150 µm  by  80 µm ) III. L INEARIZATION  M ETHOD A novel linearization approach was implemented to allowthe VTC to be used in a high resolution ADC. Severalcurrent starving devices with different gate bias voltages wereused in parallel. For simplicity, the half circuit consistingof M1, M2, M5, M7, M9, M11, and M13 is discussed. Themain current starving device, M5, is biased in saturationwhen the inverter consisting of M1 and M2 begins to makethe transition from a logic high output to logic low. M5 islinearized by using source degeneration implemented withM7. Additional current starving devices M11 and M13 areused in parallel with M5. These additional current starvingdevices are biased in the subthreshold region and enterthe moderate or heavy inversion regions when the inputsignal is sufficiently large. This mitigates the compressionof the pulse delay time versus input voltage characteristic athigh input voltages. The additional parallel current starvingdevices also increase the voltage sensitivity of the VTC. Theenhanced linearization scheme of the proposed VTC allowsit to achieve over 200 mV of dynamic range where the slopeis linear within  2%  accuracy whereas previously publishedVTC’s are highly non-linear over a similar range of inputvoltages. Simulated results in the following section show thatthe proposed linearization scheme improves the linearity andsensitivity of the VTC.IV. S IMULATED  R ESULTS  A. Voltage Sensitivity and Linearity The voltage sensitivity and linearity of the VTC were sim-ulated by sweeping the DC input of the VTC and measuringthe clock pulse delay time using a transient analysis withBSIM3v3.2 device models of a commercial  0 . 13 µm  CMOSprocess in a commercial RF simulator. The results are shownin Fig. 4 where the input voltage controls the delay of therising edges of the clock pulses rather than the falling edgesbecause the delayed pulses are measured at the output of abuffer consisting of a single inverter. For comparison, the samesimulation was repeated for a standard non-linearized VTCusing the same devices and bias voltages and for a standardVTC linearized using only source degeneration. The results areshown in Fig. 5 and Fig. 6. It can be seen that the combinationof degeneration and staggered bias parallel current starvingdevices allows the VTC to achieve highly linear performance(within  2%  of a perfectly linear slope) over an input range of 200 mV at a sensitivity of 2.5 ps/mV, and moderately linearperformance (within  25%  of a perfectly linear slope) over aninput range of 250mV. The linear range is significantly lowerfor the VTC with no linearization. Although the linearity of the VTC linearized with degeneration only is comparable tothat of the VTC with the enhanced linearization scheme, thevoltage sensitivity of the VTC with the enhanced linearizationscheme is much higher (2.5ps/mV versus 1.2ps/mV). Usingonly source degeneration for linearization and increasing thewidth of the main current starving devices, M5 and M6, doesnot result in a VTC as sensitive to the input voltage as the VTCwith the enhanced linearization scheme as demonstrated bythe simulated transient results for this case (Fig. 7). The pulseedge delay times for VTC’s with each of the four linearizationmethods considered is shown in Fig. 8 where it is evident thatthe VTC with the enhanced linearization scheme has improvedlinearity and significantly higher input voltage sensitivity thanthe other VTC’s considered. 2374  Fig. 4. Simulated transient clock pulse delay for various DC input voltagesfor the VTC using the enhanced linearization methodFig. 5. Simulated transient clock pulse delay for various DC input voltagesfor the VTC without linearization  B. Maximum Input Frequency If the VTC is used without a sample-and-hold at theinput the maximum input frequency that can be used withoutincurring a significant amount of error due to the inputsignal changing during the VTC delay time is an importantconsideration. The maximum input frequency of the VTC wassimulated by using sinusoidal input signals at multiples of the clock frequency at quarter period, half period, and threequarter period delays with respect to the clock. This allowedthe delay at sampling instants where the input signal was at aminimum, and at a maximum, and where the input signal wasat its maximum rate of change to be simulated. The simulatedresults are shown in Fig. 9 where the delay error is plottedversus input frequency at the three different sampling instants.The delay error was calculated as the difference in the outputpulse delay of the VTC compared to the output delay with aDC input voltage equal to the sinusoidal input voltage at thesampling instant. The maximum tolerable delay error due toan input signal changing rapidly during the time when thatsignal is effectively being sampled is the delay equal to oneleast significant bit (LSB) of the ADC resolution. For example,for 6 bit ADC resolution with an input dynamic range of 250mV and a sensitivity of 2.5 ps/mV, one LSB corresponds to3.9mV or a 9.76ps delay, so the maximum tolerable VTCsampling error is 9.76ps. Several lines indicating the maximumdelay error for 5 bit, 6 bit, and 7 bit ADC resolution with areshown in Fig. 9. From Fig. 9 it can be seen that for 6 bitresolution signals at frequencies up to about 1.8 GHz can beapplied directly to the VTC input for conversion to the time Fig. 6. Simulated transient clock pulse delay for various DC input voltagesfor the VTC using only source degeneration for linearizationFig. 7. Simulated transient clock pulse delay for various DC input voltagesfor the VTC using only source degeneration for linearization with the widthsof M5 and M6 increased by a factor of three 00.050.10.150.20.250.300.20.40.60.811.2x 10 −9 Input Voltage − V    C   l   o   c   k   P  u   l   s   e   E   d   g   e   D   e   l   a  y   T   i   m   e  −   s Enhanced LinearizationDegeneration OnlyDegeneration Only, 3X Wider M5, M6No Linearization Fig. 8. Simulated transient clock pulse edge delay versus input voltage forthe VTC’s with different linearization methods domain. If a resolution higher than 6 bits is required for inputfrequencies higher than 1.8 GHz then a sample-and-hold mustbe used to sample the input signal before it is applied to theVTC input. The input frequencies considered here are higherthan half the maximum clock frequency of (500MHz/2) sotime interleaving of several VTC’s in parallel could be usedto avoid sub-sampling the input frequencies (time interleavingis a technique commonly used in flash ADC’s to increase the 2375  00.511.522.533.544.5x 10 9 05101520253035Input Frequency − Hz    D  e   l  a  y   E  r  r  o  r   C  o  m  p  a  r  e   d   t  o   D   C   I  n  p  u   t  −  p  s 5 Bit Resolution7 Bit Resolution 6 Bit Resolution Max Peak Zero CrossingMin Peak Fig. 9. Simulated VTC delay error versus input frequency at various samplinginstants (at the maximum, minimum, and zero crossing of the input sinusoid) effective sampling frequency [6]). C. Noise A nonlinear periodic noise simulation was performed todetermine the noise performance of the VTC at various inputvoltages. A DC input signal was used and the input referrednoise across a  50Ω  source resistance was simulated. The sim-ulated input referred VTC spot noise at 750MHz versus inputsignal voltage is shown in Fig. 10. This input referred noiseis relatively constant over the input bandwidth of the VTCexcept in very narrow bandwidths centered around the clock frequency and the second harmonic of the clock frequency. Atthese specific frequencies there is a significant increase in inputreferred noise due to transient currents during the switchingtime of the inverter (the noise is on the order of   10 − 5 V   2 /Hz at the switching frequency). The VTC noise over most of the input bandwidth is low (on the order of   10 − 20 V   2 /Hz as shown in Fig. 10) and would not limit the resolution of an ADC using the VTC. However, VTC switching noise atthe clock frequency and its second harmonic may limit theADC resolution. The switching noise could be mitigated byusing notch filtering at the VTC input or by using switchesto disconnect the input source after the VTC has startedswitching. It should be noted that the problem of switchingnoise is common to other VTC’s using the current starvedinverter topology [5].V. C ONCLUSION A VTC with a novel linearization scheme for high speedtime-based ADC applications was designed in a  0 . 13 µm CMOS process. The slope of the delay versus voltage charac-teristic of the VTC is within  2%  of a perfectly linear slope of 2.5ps/mV over an input range of 200 mV. The performanceimprovements realized by using the linearization scheme aredemonstrated by comparing the linearity and voltage sensitiv-ity of the proposed VTC to similar VTC’s with no linearizationand linearization by source degeneration. Previously published 00.050.10.150.20.2511.522.533.54x 10 −20 VTC Input Voltage − V    I  n  p  u   t   R  e   f  e  r  r  e   d   S  p  o   t   N  o   i  s  e  a   t   7   5   0   M   H  z  −   V    2    /   H  z Fig. 10. Simulated VTC input referred noise versus input voltage VTC’s have not used linearization schemes and linearity andsensitivity results have not been published so a direct linearitycomparison with other works is not feasible. Input signals atfrequencies up to 1 GHz can be applied to the VTC withoutusing a sample-and-hold and input signals at frequencieshigher than 1 GHz can be used if the VTC is preceded bya sample-and-hold.VI. A CKNOWLEDGEMENT This work was supported by the Natural Sciences andEngineering Research Council of Canada, TRLabs, the AlbertaInformatics Circle of Research Excellence, the University of Calgary, and by CMC Microsystems.R EFERENCES[1] T. Watanabe, T. Mizuno, and Y. Makino, “An all-digital analog-to-digitalconverter with  12  −  µ v LSB using moving-average filtering,”  IEEE  Journal of Solid State Circuits , vol. 38, no. 1, pp. 120–125, Jan. 2003.[2] A. Djemouai, M. Sawan, and M. Slamani, “New 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach,”in  Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS 1999) , vol. 2, Orlando, USA, May 1999, pp. 89–92.[3] ——, “New CMOS integrated pulse width modulator for voltage con-version applications,” in  Proceedings of the 7th IEEE InternationalConference on Electronics, Circuits and Systems (ICECS 2000) , vol. 1,Jounieh, Lebanon, Dec. 2000, pp. 116–119.[4] P. Dudek and S. Szczepanski, “A high resolution CMOS time-to-digitalconverter using a vernier delay line,”  IEEE Journal of Solid State Circuits ,vol. 35, no. 2, pp. 240–247, Feb. 2000.[5] C. Gray, L. Wentai, W. V. Noije, T. H. Jr., and R. Cavin, “A samplingtechnique and its CMOS implementation with 1 Gb/s bandwidth and 25ps resolution,”  IEEE Journal of Solid State Circuits , vol. 29, no. 3, pp.340–349, Mar. 1994.[6] A. A. K. El-Sankary and M. Sawan, “New sampling method to improvethe SFDR of time-interleaved adc’s,” in  Proceedings of the IEEE In-ternational Symposium on Circuits and Systems (ISCAS 2003) , vol. 1,Bangkok, Thailand, May 2003, pp. 833–836. 2376
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