AN246 - Driving the Analog Inputs of a SAR A/D Converter | Analog To Digital Converter | Amplifier

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M Author: Bonnie C. Baker Microchip Technology Inc. AN246 For the converter shown in Figure 1, the input signal could be ac, DC or both. The operational amplifier is used for gain, impedance isolation and its drive capability. A filter of some sort (passive or active) is needed to reduce noise and to prevent aliasing errors. The ADC in Figure 1 could be external or, in the case of a SAR converter, internal to the microcontroller. The DAC / PWM block can be implemented internally or externally t
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   2003 Microchip Technology Inc.DS00246A-page 1 M AN246 INTRODUCTION Driving any A/D Converter (ADC) can be challenging if all issues and trade-offs are not well understood fromthe beginning. With Successive Approximation Regis-ter (SAR) ADCs, the sampling speed and sourceimpedance should be taken into consideration if thedevice is to be fully utilized. In this application note wewill delve into the issues surrounding the SAR Con-verter’s input and conversion nuances to insure that theconverter is handled properly from the beginning of thedesign phase. We will also review the specificationsavailable in most A/D Converter data sheets and iden-tify the important specifications for driving your SAR.From this discussion, techniques will be explored whichcan be used to successfully drive the input of the SARA/D Converter. Since most SAR applications require anactive driving device at the converter’s input, the finalsubject will be to explore the impact of an operationalamplifier on the analog-to-digital conversion in terms of DC as well as ac responses.A typical system block diagram of the SAR converter application is shown inFigure1. Some common SARconverter systems are Data Acquisition Systems,Transducers Sensing Circuits, Battery Monitoringapplications and Data Logging. In all of these systems,DC specifications are important. Additionally, therequired conversion rate is relatively fast (as comparedto Delta-Sigma converters) and having a lower number of bits that are reliably converted is acceptable. FIGURE 1: Block diagram of anapplication that has a SAR ADC in the signal  path. For the converter shown inFigure1, the input signalcould be ac, DC or both. The operational amplifier isused for gain, impedance isolation and its drive capa-bility. A filter of some sort (passive or active) is neededto reduce noise and to prevent aliasing errors.The ADC inFigure1could be external or, in the caseof a SAR converter, internal to the microcontroller. TheDAC / PWM block can be implemented internally or externally to the microcontroller as well. This function isused to drive actuators, values, etc. A filter followingthe DAC / PWM function is usually required to performa smoothing function. This filter would reduce glitcherrors, quantization errors and provide drive or isolationto the actuator. In this discussion we will focus on theinput section to the A/D Converter. BASIC OPERATION OF THE SAR ADC With the SAR ADC, the input signal should be consid-ered in the DC as well as ac domain. This is true evenif you are only interested in a DC response. DC Errors of the SAR ADC The offset and gain errors of an ADC can be easily cal-ibrated out of the resulting data using the microcontrol-ler at the output of the converter. But the more difficultDC errors to calibrate out would be Integral Non-Lin-earity (INL) and Differential Non-Linearity (DNL). Inmost systems, these errors manifest themselves asincorrect conversions or noise. Of the two specifica-tions, INL is the “Holy Grail” of DC specificationsbecause it describes the entire transfer function. INL isa measure of how close to actual the transition pointsare to the ideal transfer function. This is a difficult error to calibrate out with a microcontroller because everycode needs to be evaluated for proper calibration andthis error differs from device to device.While noise is usually not a topic for DC accuracy, inthis case it has merit. It is important to realize that theSAR ADC operates in the frequency domain. This istrue even though you may think that you are measuringnear DC signals. If there is a noise source in the sys-tem, the “DC” conversion from sample-to-sample maynot be the same. This phenomena is reduced by usinganti-aliasing filters. When digitizing AC signals, other characteristics of the converter come into play. Thesecharacteristics include distortion of the input signal andnoise levels. Anti-aliasing filters are also useful for these type of problems.  Author:Bonnie C. Baker Microchip Technology Inc. Filter AmpFilter Micro-controller EngineOutputInputSignalSourceAnalog toDigitalConverter DAC or PWM Driving the Analog Inputs of a SAR A/D Converter  AN246 DS00246A-page 2  2003 Microchip Technology Inc. Basic SAR ADC Operation At the input of a SAR ADC, the signal first sees a switchand a capacitive array, as shown inFigure2. Thecapacitors in this array are all connected to each other with the input signal node on one side and the non-inverting input to a comparator on the other. FIGURE 2: Model of the MCP320X 12-Bit ADC. Once the input signal has been sampled to the internalcapacitive array of the converter, the switch is open andthe bottom side of the MSb capacitor is connected toV REF , while the other capacitors are tied to V SS (or thesystem ground). With this action, the charge from theMSb capacitor is redistributed among the other capac-itors. The non-inverting input of the comparator movesup or down in voltage according to the way the chargeis distributed. The voltage at the non-inverting input of the comparator, with respect to V SS , is equal to(1/2V DD -V IN ) + 1/2V REF . If this voltage is greater than1/2V DD , an MSb equal to zero is transmitted out of theserial port synchronized with SCLK through S DOUT andthe MSb capacitor is left tied to V REF . If this voltage isless than 1/2V DD , a MSb bit equal to one is transmittedout of the serial port and the MSb capacitor isconnected to V SS .With the determination of the value of the MSb, theconverter then examines the MSb-1 value. This is doneby connecting the MSb-1 capacitor to V REF , while theother capacitors are tied to V SS (except for the MSbcapacitor). Since you will note that the MSb-1 capacitor is not illustrated inFigure2,its value is 8C. With thisaction, the value of the voltage at the non-invertinginput of the comparator is [1/2V DD - V IN ] + 1/2V REF (MSb) + 1/4V REF . Once again, a comparison of thisvoltage to 1/2V DD is performed with the comparator. Inthis analysis, if this voltage is greater than 1/2V DD , thena MSb-1 equal to zero is transmitted out of the serialport through S DOUT and the MSb-1 capacitor is left tiedto V REF . If this voltage is less than 1/2V DD , a MSb-1 bitequal to one is transmitted out of the serial port and theMSb-1 capacitor is connected to V SS . This process isrepeated until the capacitive array is fully utilized. Effects of Input Source Resistance A detailed model of the internal input sampling mecha-nism of a SAR ADC is shown inFigure3. The criticalvalues to pay attention to in this model are R S ,C SAMPLE and R SWITCH . C SAMPLE models the summa-tion of the capacitive array shown inFigure2. Errorsdue to the pin capacitance and leakage are minimal.The internal switch resistance combines with the exter-nal source resistance and sample capacitor to form aR/C pair. This R/C pair requires approximately 9.5 timeconstants to fully change to 12-bits over temperature.For the MCP3201 12-bit A/D Converter, 938nsec arerequired to fully sample the input signal assumingR S <<R SWITCH . FIGURE 3: The model of the input stageof the MCP320X ADC can be reduced to a switchresistance and sample capacitor. The accuracy of a SAR ADC, such as the 12-bitMCP3201, can be compromised if the device is notgiven enough time to sample. In the graph of Figure4,the y-axis is Clock Frequency in MHz and the x-axis isInput (Source) Resistance in ohms. The sampling timeof the converter for these clock frequencies is equal to1.5clocks. For example, a clock speed of 1.6MHzwould translate to a sample time of (1.5/1.6MHz) or 937.5nsec. FIGURE 4: This graph is plotted to indi-cate where the MCP3201 will continue to operateaccurately with in 0.1LSb. V IN 16C2C4C6CV REF 1/2V DD S C + _ SARControlLogicR SAMPLE 1k Ω Shift Register V SS SCLKCSS DOUT Cap array is both thesample cap and a DACAnalogInputR SOURCE MCP3201 R SW = 1k Ω C SAMPLE =25pFV SS C PIN =7pFV CAP ~R SOURCE   R SW  + ( ) C  SAMPLE  ×  Rise Time of Voltage on C  SAMPLE  0.00.20.40.60.81.01.21.41.61.8100100010000 Input Resistance (Ohms)    C   l  o  c   k   F  r  e  q  u  e  n  c  y   (   M   H  z   ) V DD = V REF = 5VV DD = V REF = 2.7V   2003 Microchip Technology Inc.DS00246A-page 3 AN246 In order to keep the source resistance low, it is recom-mended that the converter be driven by an active ele-ment, such as an operational amplifier. In this situation,the input signal could be ac, DC or both. The opera-tional amplifier can be used for gain, filtering, imped-ance isolation and its drive capability. When you drivethe input of an ADC with an operational amplifier,whether it is a gain cell, filter cell or both, offset, noise,gain errors and distortion can be added to the signalprior to the ADC by the amplifier. The investigation of these issues as they relate to the conversion processfollows.Figure4illustrates how the source resistance to theADC can cause conversion errors. There are two obvi-ous solutions to the problem. One would be to reducethe source resistance, while the second would be toincrease the sampling time. AC Performance of the ADC The ac performance of an ADC can easily be viewed bylooking at the FFT results from multiple, periodic con-versions. An FFT plot is produced through mathemati-cal calculations performed on a series of repetitivesamples. In this calculation, the data is “binned” out intofrequencies. The resultant graph produced illustratesthe magnitude of the signal frequencies that go throughthe converter. FIGURE 5:  An FFT plot is used toevaluate an ADC performance over frequency. From this calculation, we can extrapulate the funda-mental input signal, the harmonics above that signaland the noise floor. These calculations not only give agraphical representation of the signal through the con-verter, they also allow for the calculation of theSpurious Free Dynamic Range, Effective Number of Bits and Signal-to-Noise Ratio. Refer to AN681, “Read-ing and Using Fast Fourier Transforms (FFT)”, for moreinformation on FFTs.Although this graph presents a considerable amount of information, the plot does not differentiate aliasedsignals from real signals. IMPACT OF THE OPERATIONALAMPLIFIER We will start with the operational amplifier block showninFigure6and discuss its characteristics as they relateto this application. FIGURE 6: The ideal operational ampli-fier description can be separated into four basic categories: input, power supply, output and signal transfer. While the operational amplifier brings features that aredesirable to this application, there are trade-offs toaccount for in the design. In terms of DC parameters,the operational amplifier will have some limitations withits input and output swings. Additionally, if the wrongoperational amplifier is selected, it may not be able todrive the ADC at the speeds required in the conversionprocess. With noise being an additional error contrib-uted by any element put in the signal path, the opera-tional amplifier is no exception. The ADC will alsogenerate its own noise. The trick we will learn is that theoperational amplifier noise must simply be lower thanthe ADC noise to be useful. Finally, the distortion char-acteristics of the operational amplifier should be con-sidered. Characteristics like the bandwidth of theoperational amplifier and the harmonic distortion near the output rails are candidates for possible degradationof the signal as it travels through the data acquisitionsystem.A = Fundamental Input SignalB = HeadroomC = Signal-to-Noise RationD = Spurious Free Dynamic RangeE = Average Noise Floor  INPUTã Input Current (I B ) = 0ã Input Impedance (Z IN ) = ∞ ã Input Voltage Range (V IN ) → no limitsã Zero Input Voltage and Current Noiseã Zero DC Offset Error (V OS )ã Common-Mode Rejection = ∞ POWER SUPPLYã No min or max Voltage (V DD , V SS )ã I SUPPLY = 0 Ampsã Power Supply Rejection Ratio (PSRR) = ∞ SIGNAL TRANSFERã Open Loop Gain (AOL) = ∞ ã Bandwidth = 0 → ∞ ã Zero Harmonic Distortion (THD)OUTPUTã V OUT = V SS to V DD ã I OUT ã Slew Rate (SR) = ∞ ã Z OUT = 0 Ω V DD V SS V IN - V IN+ V OUT OpAmp  AN246 DS00246A-page 4  2003 Microchip Technology Inc. Operational Amplifier Input Stage Each of the two input pins of the operational amplifier has voltage swing restrictions. These restrictions aredue to the input stage design and the power supply lim-itations. In the device product data sheet, the input volt-age restrictions are clearly defined as the Input VoltageRange and is a separate line item in the specificationtable, or as a condition for the CMRR specification(Input Common-Mode Voltage Range, VCM). Themore conservative specification of the two is where theinput voltage range is called out as a CMRR test condi-tion because the CMRR test validates the Input VoltageRange in test.The higher input voltage range is more a function of theinput circuit topology than it is the silicon process.Again, the product data sheet should be referred to for clarification on how your selected operational amplifier performs across the input range of the operationalamplifier.Operational amplifiers that do not span across theentire power supply voltage range on the input are notuseless. As a matter of fact, these operational amplifi-ers are useful in most circuits except for buffer configu-rations. Otherwise, if you use these operationalamplifiers with a gain of two or higher, you can easilyget around the fact that the operational amplifier doesnot have a rail-to-rail input range. Operational Amplifier Noise Contribution Operational amplifier device noise falls into two catego-ries: voltage noise and current noise. Voltage noise isusually specified for all operational amplifiers over thefull frequency range, while current noise may or maynot be specified for the lower input current devices,such as CMOS amplifiers or FET input amplifiers, butis always specified for Bipolar input amplifiers. Themagnitude of the operational amplifier noise is depen-dant on the input structure and the amount of currentbeing driven internally through that structure.Noise is gaussian in nature. It is close enough to a nor-mal distribution that many of the calculations todescribe a normal distribution are used to describegaussian noise. For instance, gaussian noise units canbe described as root mean square (RMS). This couldbe considered analogous to the calculation of one stan-dard deviation, referred to as normal distributions. TheRMS noise can be referred to the input (RTI) of the cir-cuit or operational amplifier. It can also be referred tothe output (RTO). When refering to the output, theoperational amplifier gain is included in the RMS num-ber. When defining peak-to-peak noise, a multiplier called the crest factor is used. This multiplier is usedwhen describing non-correlated events like noise. Spotnoise will be defined in the next paragraph of thisapplication note.Spot noise is the last unit of measure that you will findwith noise specifications. Spot noise can be found inthe noise density plots of product data sheets.Essentially, spot noise is the noise contributed by theoperational amplifier in a particular 1Hz frequencybandwidth. Spot noise is specified in volts or amperes.In both cases, the denominator of these units is asquare root of Hertz. This parameter, typically, isreferred to the input of the operational amplifier anddefined at a particular frequency. To calculate the noisecontributed by the operational amplifier across a spec-ified bandwidth, the area under this curve is calculated.This representation of noise provides the flexibilityneeded to calculate total noise for various gains andsystems.The first step to determining the theoretical RMS or peak-to-peak noise is to calculate the closed loop gainof the noise signal. This may or may not be differentthan the signal gain. The noise gain is calculated as if there were a signal source at the non-inverting input of the operational amplifier. The area under the noisedensity curve is calculated and multiplied by the closedloop gain of the circuit.The area under the noise density curve should be cal-culated in a piece wise manner. One region is acrossthe 1/f noise region of the noise density curve. The sec-ond segment is located where the noise density curveand the operational amplifier gain curve are flat. Thethird region would be where the operational amplifier curve is starting to fall at 20dB per decade. In all cases,these areas are multiplied by the square root of thebandwidth of interest.The different regions are added with a square root of the sum of the squares formula to obtain the entirenoise contribution of the circuit. The calculated value inthis exercise is the referred to output (RTO) noise in theunits V rms . A way to view this noise on the bench is touse a scope and look at the output of the operationalamplifier. While the scope photo would not have anysignificant frequency content, it would, in fact, show a“noisy” view on the screen. Your calculated RMS num-ber would be equivalent to a line at approximately 70%of this signal, centered on the median of the noise onthe scope screen.This type of noise is a statistical occurrence. Hypothet-ically, one would have to wait an infinite amount of timeto determine whether or not the designed system wouldremain within a set of boundaries. This approach todetermining the peak-to-peak noise in a circuit is fairlyunreasonable, but because we have characterized thisnoise as gaussian in nature, we can use a statisticalmodel to predict the peak-to-peak noise with a degreeof certainty.The technique of predicting the peak levels of noise isrelatively simple to calculate using a crest factor. If acrest factor is identified, multiplied by 2 times the RMSvalue, the peak-to-peak noise response of the systemcan be determined with a level of certainty.
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