DC, LF dispersion and hf characterisation of short time stressed inp based LM-HEMTS

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DC, LF dispersion and hf characterisation of short time stressed inp based LM-HEMTS
  ~) Pergamon Microelectron. Reliab., Vol. 36, No. 11/12, pp. 1911-1914, 1996 Copyright © 1996 Elsevier Science Ltd Printed in Great Britain. All rights reserved 0026-2714/96 15.00+.00 PII: S0026-2714(96)00227-2 DC, LF DISPERSION AND HF CHARACTERISATION OF SHORT-TIME STRESSED INP BASED LM-HEMTS D. SCHREURS 1 A. SPIERS 2, W. DE RAEDT 3, K. VAN DER ZANDEN 3, Y. BAEYENS 1 M. VAN HOVE 3, B. NAUWELAERS 1 and M. VAN ROSSUM 3 1 K.U.Leuven, Div. ESAT-TELEMIC, Kard. Mercierlaan 94, B-3001 Heverlee, Belgium 2 KaHo St.-Lieven, KIHO, Gebr. Desmetstraat 1, B-9000 Gent, Belgium 3 IMEC, Div. ASP/CSP, Kapeldreef 75, B-3001 Heverlee, Belgium Abstract: InP based LM-HEMTs are stressed at room temperature in a minute time- frame. Depending on the applied DC bias, various failure mechanisms are favorised. Their influence on the device characteristics is measured and analysed. A significant change in the DC and HF parameters has been noticed when stressed in the impact ionization region, which is not recoverable. However, after stress in the avalanche region only the gate leakage current increased and this is recoverable after a few min- utes. During stress in both regions, the gate current/as and the drain current lds vary on a logaritmic time scale. This enlightens the importance of possible influence of standard on-wafer DC and HF characterizations on the device performance. Copyright © 1996 Elsevier Science Ltd INTRODUCTION Due to the saturation of the lower frequency bands, a shift to the millimetre wave region is expected to solve the problem of the increasing demand in frequency allocation. At present, AllnAs/InGaAs High Electron Mobility Transistors (HEMTs) grown on InP substrates have shown to be the best performing three terminal devices: very low-noise figures and high gain have been achieved up to 100 GHz and above [1 ]. The millimetre wave market for components, circuits and systems based on InP compounds is still small, but growing together with the maturing of the InP technology. This necessitates a thorough study of the reliability issues of InP based HEMTs. Up to now, only little reliability data is available. Moreover, reliability testing is mostly limited to thermal stress [2,3]. We will present the results of short time biasing stresses on InP HEMTs at room temperature. In section II, the InP HEMT technology at IMEC will be given. A general experiment at vari- ous bias conditions will be described and analysed in section III. In section IV, we will focus more in detail to the most relevant failure mechanisms for the considered stress conditions, which are gate-drain avalanche and drain-source impact ionization. INP HEMT TECHNOLOGY The studied InP based HEMTs are passivated lattice-matched (LM) AllnAs/InGaAs HEMTs, op- timized for low-noise millimetre wave applications. The gate-drain breakdown voltage is 3.5V. 1911  1912 D. Schreurs et al. Table 1 compares the performance of 0.15 #m gatelength LM and pseudomorphic (PM) InP with PM GaAs devices. This table clearly shows the superiority of InP in terms of extrinsic fT, fm,~, microwave gain and noise figure. More details about the IMEC InP technology can be found in [4]. Table 1: Figures of merit of 0.15 #m HEMTs measured before passivation. GaAs PM-HEMT InP LM-HEMT InP PM-HEMT ext. fT [GHz] 120 160 190 ext. fma~ [GHz] 160 300 350 MAG@26 GHz [dB] 14.5 19.3 20.3 NFmin@26 GHz [dB] 1.1 0.9 n.a. BIASING STRESS EXPERIMENT We will first describe a general biasing test experiment applied to a InP LM-HEMT. The DC char- acteristics have been measured before and after the standard procedure to determine a non-linear HEMT model [5]. This involves S-parameter measurements at biases across the whole Vg,-Vd~) bias plane. These measurements have been performed on-wafer at room temperature, whereby the HEMTs are exposed to air. S-parameter measurements have been performed at extrinsically ap- plied Vg~ ranging from -1.3 V to 0.35 V and Vds ranging from 0 V to 2.8 V. The total duration of 1271 S-parameter measurements and data processing was about 5 hours or about 14s stress at each bias point. Figure 1 shows Id~ and Ig~ before and after the experiment. We notice a significant decrease of both [Id~ and I These DC characteristics were not recovered after 72 hours. 0.0 -'+00 Vds [V] I 9E*00 i I J i i -1,3E*00 VgslV] 150.~E-03 Figure h Iris and lgs before (+) and after (_) DC- and HF-stress on a 0.2 #m, 150 #m InP LM- HEMT (intrinsic Vgs=-1.3 V... 0.15 V, intrinsic Vd~=0 V... 1.9 V). Since during this stress various biases are applied of which each can favorise a particular failure mechanism, the device degrades gradually during the test. The contribution of HF stress is minor, because of the low power applied (< -20 dBm). We threat those failure mechanisms that have a significant influence on the device performance within the time period of a normal S-parameter measurement frequency sweep (< 1 minute). Effects due to the channel temperature increase dur- ing bias are kept very limited and will not cause any contact degradation. ANALYSIS OF THE FAILURE MECHANISMS We focus to the extreme bias conditions applied in the previous test. We applied these bias condi- tions for 90s, during which Igs and lds were measured continuously, lg~ and ld~ remained constant as a function of time during stress at the bias corresponding to turn-on of the gate-source Schottky  InP based LM-HEMTs 1913 diode (Vjs=0.4 V, Vds=l V). At the bias condition below pinch-off and slightly above gate-drain breakdown (Va,=- 1 V, Vds =3 V), I as I and I d~ I increase respectively 11% and 6% as a function of time due to avalanching (Figure 2). The DC characteristics after this stress remained unchanged, apart from a 10% increase in reverse gate leakage current. The normal value is recovered after about one minute. The third considered bias condition is at maximum gm and slightly above gate- drain breakdown (Vas=-0.5 V, Vd~=3.5 V). This is in the impact ionisation region since the corre- sponding Ia~ for this device shows the typical bell shape. Impact ionisation is apparently dominant to the gate-drain avalanching since I 1 as I and lids decrease respectively 46% and 9% as a function of time (Figure 2). Figure 3 presents the DC Ida, gm and Ijs at a normal operating bias condition before and after this stress. Table 2 summarizes the DC and HF performance parameters. I, tss~t is decreased by 3% and the gate-drain capacitance Cad is smaller, which are typical observations for impact ionization stress [6]. Also a small negative V shift is observed of which the physical cause is still unclear. When measured at a constant lds, the decrease of both the DC gm and HF gm is 3.5%. This means that the g~ dispersion characteristic is unchanged. This has been confirmed by LF-dispersion measurements up to 100 kHz using a measurement system based on a lock-in am- plifier. Also, only a minor difference has been noticed in the DC characteristics measured under dark and light illumination. This means that, although significant dispersion related degradation effects may occur in unpassivated devices, the dispersion in these passivated devices is small. <ooo 0~ u~ tm,r~ HH .o i.ii ............ ........... .......... .......... ........... ........... ........... . .......... ........... ........... ~~~-~'-i ............ i ........... :: i A O.0E÷00 time [s] 93.0E 00 Ill ........... : ........... i ........... ~ ............ : ........................ ~ ........... i ........... ~ ............ ~ ........... 0.0E 00 time [s] 91.0E 00 Figure 2: Ijs (t3) and lds (+) of a 0.2 m, 50 m InP LM-HEMT versus time at (left) gate-drain avalanche bias condition (Vas=-I V, Vds=3V) and (right) drain-source impact ionization bias con- dition (Vg~=-0.5V, Vds=3.5V). o.T= o~ m ............ ........... ':T ........... ~~ ~I~i -1.3E+00 ~;.......iiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii ..... Vgs [V] 150.0E 03 o F i '7~ ......... ~ i :: ~ i ~ : ....... ~ ............ ......................... i ............ ............ i ........... l ...... ~ i ..... -1.3E+00 Vgs IV] 150.0E~03 Figure 3: la8, gm and Ig~ at Vd~=0.7 V before (+) and after (_) DC-stress at (Vgs=-0.5V, Vd,=3.5V) on a 0.2 m, 50 m InP LM-HEMT.  1914 D. Schreurs et al. Table 2: Performance parameters before and after biasing stress at (Vas=-0.5V, Vas=3.5V). VT Iassat DC gm@10mA HFgm@10mA Cg~@10mA fT IV] [mA/mm] [mS/mm] [GHz] [fF/mm] [GHz] before stress - 1.02 518 708 695 240 102 after stress - 1.08 503 684 669 220 98 From this analysis, we conclude that the most important bias conditions during non-linear model device extraction that have a significant influence on the device behaviour are those corresponding to drain-source impact ionisation. This shows the importance of user device knowledge when per- forming standard DC and HF characterisation measurements. CONCLUSIONS InP based LM-HEMT devices are stressed at room temperature for a few minutes. During this small period, changes in the device characteristics are especially noticeable at biases corresponding to the gate-drain avalanche region and the drain-source impact ionization region. The first stress condi- tion implies an increase in gate leakage, but this is recoverable after a few minutes. Stress in the impact ionization region is permanent and is accompanied by a significant influence on the device's DC and HF characteristics. Since the stress influence is a logaritmic function of time, its importance during standard on-wafer DC and HF device characterization at room temperature is not negligible. ACKNOWLEDGEMENTS The authors wish to express their gratitude to the complete staff of ESAT-TELEMIC and ASP/CSE The financial support of ESA and IWT are acknowledged. D. Schreurs is supported by the National Fund for Scientific Research as a Research Assistant. REFERENCES 1. L.D. Nguyen, A.S. Brown, M.A. Thompson and L.M. Jelloiah, 50-nm Self-Aligned-Gate Pseu- domorphic AllnAs/GalnAs High Electron Mobility Transistors, IEEE Trans. Electron Devices, Vol. 39, 2007-2014 (1992) 2. M. Tutt, G.I. Ng, D. Pavlidis and J. Mansfield, Reliability Issues of InAIAs/InGaAs High-Elec- tron-Mobility Transistors, Proc. 3 th Int. Conf. on lnP and R el. Mat., 349-352 (1991) 3. Y. Ashizawa, C. Nozaki, T. Noda, A. Sasaki and S. Fujita, Surface related degradation of InP- based HEMTs during thermal stress, Solid-State Electronics, Voi. 38, No. 9, 1627-1630 (1995) 4. M. Van Hove, J. Finders, K. van der Zanden, W. De Raedt, M. Van Rossum, Y. Baeyens, D. Schreurs, B. Nauwelaers, A. Zeng and M.K. Jackson, InP-Based HEMT Technology for MMIC Applications, 23rd State-of-the-Art Program on Compound Semiconductors SOTAPOCS XXIII); October 8-13, Chicago, USA, (ECS Proceedings. Vol. 95-21.), 395-407 (1995) 5. D. Schreurs, Y. Baeyens, B. Nauwelaers, W. De Raedt and M. Van Rossum, Automated gen- eration of intrinsic large-signal HEMT models from S-parameter measurements, Microwave and Optronics Conference, Sindelfingen, Germany, 30 May-I June, 106-110 (1995) 6. R. Menozzi, P. Cova, C. Canali, E Fantini, Breakdown Walkout in Pseudomorphic HEMT's, IEEE Trans. Electron Devices, Vol. 43, No. 4, April, 543-546 (1996)
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